// ---- Created with 3Dmigoto v1.2.35 on Tue Apr 26 22:30:56 2016



// 3Dmigoto declarations
#define cmp -
Texture1D<float4> IniParams : register(t120);
Texture2D<float4> StereoParams : register(t125);


void main( 
  float4 v0 : POSITION0,
  float4 v1 : COLOR0,
  float4 v2 : COLOR1,
  float4 v3 : COLOR2,
  float4 v4 : COLOR3,
  float4 v5 : COLOR4,
  float4 v6 : TEXCOORD0,
  float4 v7 : TEXCOORD1,
  float4 v8 : TEXCOORD2,
  float4 v9 : TEXCOORD3,
  float4 v10 : TEXCOORD4,
  float4 v11 : TEXCOORD5,
  float4 v12 : TEXCOORD6,
  float4 v13 : TEXCOORD7,
  out float4 o0 : POSITION0,
  out float4 o1 : COLOR0,
  out float4 o2 : COLOR1,
  out float4 o3 : COLOR2,
  out float4 o4 : COLOR3,
  out float4 o5 : COLOR4,
  out float4 o6 : TEXCOORD0,
  out float4 o7 : TEXCOORD1,
  out float4 o8 : TEXCOORD2,
  out float4 o9 : TEXCOORD3,
  out float4 o10 : TEXCOORD4,
  out float4 o11 : TEXCOORD5,
  out float4 o12 : TEXCOORD6,
  out float4 o13 : TEXCOORD7)
{
}

/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Original ASM ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
//
// Generated by Microsoft (R) HLSL Shader Compiler 9.30.9200.20546
//
//
//
// Patch Constant signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// SV_TESSFACTOR            0   x           0 QUADEDGE   float   x   
// SV_TESSFACTOR            1   x           1 QUADEDGE   float   x   
// SV_TESSFACTOR            2   x           2 QUADEDGE   float   x   
// SV_TESSFACTOR            3   x           3 QUADEDGE   float   x   
// SV_INSIDETESSFACTOR      0   x           4  QUADINT   float   x   
// SV_INSIDETESSFACTOR      1   x           5  QUADINT   float   x   
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyzw        0     NONE   float   xyzw
// COLOR                    0   xyzw        1     NONE   float   xyzw
// COLOR                    1   xyzw        2     NONE   float   xyzw
// COLOR                    2   xyzw        3     NONE   float   xyzw
// COLOR                    3   xyzw        4     NONE   float   xyzw
// COLOR                    4   xyzw        5     NONE   float   xyzw
// TEXCOORD                 0   xyzw        6     NONE   float   xyzw
// TEXCOORD                 1   xyzw        7     NONE   float   xyzw
// TEXCOORD                 2   xyzw        8     NONE   float   xyzw
// TEXCOORD                 3   xyz         9     NONE   float   xyz 
// TEXCOORD                 4   xy         10     NONE   float   xy  
// TEXCOORD                 5   xyzw       11     NONE   float   xyzw
// TEXCOORD                 6   xyzw       12     NONE   float   xyzw
// TEXCOORD                 7   xyzw       13     NONE   float   xyzw
//
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// POSITION                 0   xyzw        0     NONE   float   xyzw
// COLOR                    0   xyzw        1     NONE   float   xyzw
// COLOR                    1   xyzw        2     NONE   float   xyzw
// COLOR                    2   xyzw        3     NONE   float   xyzw
// COLOR                    3   xyzw        4     NONE   float   xyzw
// COLOR                    4   xyzw        5     NONE   float   xyzw
// TEXCOORD                 0   xyzw        6     NONE   float   xyzw
// TEXCOORD                 1   xyzw        7     NONE   float   xyzw
// TEXCOORD                 2   xyzw        8     NONE   float   xyzw
// TEXCOORD                 3   xyz         9     NONE   float   xyz 
// TEXCOORD                 4   xy         10     NONE   float   xy  
// TEXCOORD                 5   xyzw       11     NONE   float   xyzw
// TEXCOORD                 6   xyzw       12     NONE   float   xyzw
// TEXCOORD                 7   xyzw       13     NONE   float   xyzw
//
// Tessellation Domain   # of control points
// -------------------- --------------------
// Quadrilateral                           1
//
// Tessellation Output Primitive  Partitioning Type 
// ------------------------------ ------------------
// Clockwise Triangles            Integer           
//
hs_5_0
hs_decls 
dcl_input_control_point_count 1
dcl_output_control_point_count 1
dcl_tessellator_domain domain_quad
dcl_tessellator_partitioning partitioning_integer
dcl_tessellator_output_primitive output_triangle_cw
dcl_hs_max_tessfactor l(3.000000)
dcl_globalFlags refactoringAllowed
dcl_immediateConstantBuffer { { 1.000000, 3.000000, 0, 0},
                              { 0, 1.000000, 0, 0},
                              { 0, 3.000000, 0, 0},
                              { 0, 1.000000, 0, 0} }
hs_control_point_phase 
dcl_input v[1][0].xyzw
dcl_input v[1][1].xyzw
dcl_input v[1][2].xyzw
dcl_input v[1][3].xyzw
dcl_input v[1][4].xyzw
dcl_input v[1][5].xyzw
dcl_input v[1][6].xyzw
dcl_input v[1][7].xyzw
dcl_input v[1][8].xyzw
dcl_input v[1][9].xyz
dcl_input v[1][10].xy
dcl_input v[1][11].xyzw
dcl_input v[1][12].xyzw
dcl_input v[1][13].xyzw
dcl_output o0.xyzw
dcl_output o1.xyzw
dcl_output o2.xyzw
dcl_output o3.xyzw
dcl_output o4.xyzw
dcl_output o5.xyzw
dcl_output o6.xyzw
dcl_output o7.xyzw
dcl_output o8.xyzw
dcl_output o9.xyz
dcl_output o10.xy
dcl_output o11.xyzw
dcl_output o12.xyzw
dcl_output o13.xyzw
mov o0.xyzw, v[0][0].xyzw
mov o1.xyzw, v[0][1].xyzw
mov o2.xyzw, v[0][2].xyzw
mov o3.xyzw, v[0][3].xyzw
mov o4.xyzw, v[0][4].xyzw
mov o5.xyzw, v[0][5].xyzw
mov o6.xyzw, v[0][6].xyzw
mov o7.xyzw, v[0][7].xyzw
mov o8.xyzw, v[0][8].xyzw
mov o9.xyz, v[0][9].xyzx
mov o10.xy, v[0][10].xyxx
mov o11.xyzw, v[0][11].xyzw
mov o12.xyzw, v[0][12].xyzw
mov o13.xyzw, v[0][13].xyzw
ret 
hs_fork_phase 
dcl_hs_fork_phase_instance_count 4
dcl_input vForkInstanceID
dcl_output_siv o0.x, finalQuadUeq0EdgeTessFactor
dcl_output_siv o1.x, finalQuadVeq0EdgeTessFactor
dcl_output_siv o2.x, finalQuadUeq1EdgeTessFactor
dcl_output_siv o3.x, finalQuadVeq1EdgeTessFactor
dcl_temps 1
dcl_indexrange o0.x 4
mov r0.x, vForkInstanceID.x
mov o[r0.x + 0].x, icb[r0.x + 0].y
ret 
hs_fork_phase 
dcl_hs_fork_phase_instance_count 2
dcl_input vForkInstanceID
dcl_output_siv o4.x, finalQuadUInsideTessFactor
dcl_output_siv o5.x, finalQuadVInsideTessFactor
dcl_temps 1
dcl_indexrange o4.x 2
mov r0.x, vForkInstanceID.x
mov o[r0.x + 4].x, l(1.000000)
ret 
// Approximately 21 instruction slots used

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~*/
